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For the von Neumann machine, the accumulator is instructed to obtain
the first byte of data from input, then write the byte to memory,
then read a byte of data from input, then write a byte to memory,
etc. until all bytes have been read from input, through the accumulator,
and then written to memory, all under constant direction from the
control unit.
For the bus machine, on the other hand, the CPU directs the input
device to write 100 bytes to such and such an address in memory,
and to signal the CPU when the input is complete. During this time,
the CPU is free to perform other tasks and use the bus when it is
not being used for other input or output operations. When the
signal is received by the CPU indicating the 100 bytes have been
read, the CPU then instructs the output device to read 100 bytes
from such and such an address in memory, and then to signal the
CPU when the output is complete.
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Okay, there wasn't really such a machine, but if there were, here's
how it would have worked. The program would include 3 addresses
each representing the start of an array "hard coded" in the program,
along with the address of a counter and a size for the arrays.
We assume that the value at address counter is initially zero.
The steps in the program went something like this:
- Load the data stored at address A into the accumulator,
- add the data stored at address B to the accumulator,
- save the data in the accumulator to address C.
- Load the address which stores the address of A (i.e., the address of
the address in the load in struction in step "a" above) into the accumulator,
- add 1 to the accumulator,
- save the data in the accumulator to the address which stores the
address of A.
- Load the address which stores the address of B into the accumulator,
- add 1 to the accumulator,
- save the data in the accumulator to the address which stores the
address of B.
- Load the address which stores the address of C into the accumulator,
- add 1 to the accumulator,
- save the data in the accumulator to the address which stores the
address of C.
- Load the data stored at the address containing the counter into the accumulator,
- add 1 to the accumulator,
- save the data in the accumulator to the address of the counter.
- if the data in the accumulator is less than the counter,
jump to step "a".
- halt.
In other words, we simply increment the 3 addresses IN THE PROGRAM,
allowing us to "loop through" the arrays as we "loop through" the program.
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With Charlie's approach, there would be a fairly complex program
written for each target machine/operating system which converted
the SDL into Level 3 code for that machine. Although some of
the code would be identical for all such translators
(scanning and parsing, for example), there would certainly be
platform specific code for each target. The code produced could
be optimized for the target platform.
With Ray's approach, there would be essentially two programs, one
which translates the SDL into an intermediate language, and one which
interprets this intermediate language on a particular platform.
The first program would be somewhat less complicated than any of
the programs needed under Charlie's approach. The second program
would be implement a virtual machine interpreter for the intermediate
language. Under Ray's approach, both programs (the translator and
the interpreter) would need to be ported to most target platforms,
but the difficulty of porting would be somewhat less than that
of porting Charlie's program. By carefully choosing the design
of the intermediate language, the size of the intermediate programs
could be minimized. Optimization for any particular platform
would occur only in the interpreter. The code produced would not
likely be as fast as under Charlie's scheme (due to the extra layer
of interpretation), but there would be less of it.
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First, we note that in the original design, 12 microinstructions take 300
nanoseconds, 12,000 microinstructions take 300 microseconds, 12,000,000
take 300 milliseconds, and 1,200,000,000 (or 100,000,000 conventional
machine instructions) take 30 seconds.
If only the hardware team succeeds, the time is reduced by a factor
of 20/25 (i.e., 4/5), resulting in 24 seconds.
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If only the microcode team succeeds, the number of instructions
required is reduced by
a factor of 10/12 (i.e., 5/6), resulting in 25 seconds.
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If both teams succeed, the time is reduced by both factors, 20/25 and 10/12,
for a net factor of 2/3, resulting in 20 seconds.
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Yes, since the speedup was by a factor of 1/3 (33 1/3%).